1. Field of the Invention
The present invention relates to integrated circuits, and more specifically to surround-gate semiconductor devices in which the gate region coats the channel region.
2. Description of Related Art
Among “surround-gate” devices, we may distinguish devices with a double-gate in which the gate region has two parts, and those known as Gate All Around (GAA) in which the gate region is formed of a single part coating the channel region.
Surround-gate devices, whether with a double-gate or not, are particularly advantageous for channel lengths of less than 50 nanometers, since they make it possible to eliminate short channel effects while making it possible to obtain a doubled or tripled current strength relative to a conventional transistor. It may be recalled at this point that a short channel has a very short distance (length) between the source and the drain, and that the “short channel effect” is expressed by a reduction in the threshold voltage of the transistor, which may ultimately lead to obtaining a transistor which is very difficult to control and result in “drill” mode.
Different solutions are known for manufacturing double-gate semiconductor devices. A first solution consists of using a well known technique of molecular bonding to make on a semiconductor substrate a stack of layers including a first gate material layer topped by an insulating layer topped by a silicon layer topped by another insulating layer itself topped by a second gate material layer. This stack is anisotropically etched in order to define a pillar comprising the future bottom gate of the transistor insulated from the silicon layer (channel) by a dielectric layer, and the future top transistor gate supported by the channel and insulated from it by the other dielectric layer. The source and drain regions are then formed by a selective silicon epitaxy.
Such a solution has drawbacks. Among these is the fact that the source, channel, and drain regions are not formed with the same original silicon since the source and drain regions are the result of a further epitaxy. In fact such further epitaxy does not allow, given the surface prior cleaning problems, the form of the source and drain regions to be accurately controlled, which does not allow the value of the source and drain access resistances to be controlled very accurately.
Additionally, by virtue of this further epitaxy, the source and drain regions are bubble shaped, which requires that the necessary space be provided for these bubbles to form. Moreover, such a shape induces risks of leaks between the bottom gate and these source and drain regions.
Another solution consists in not totally etching the stack of layers initially formed on the substrate. More specifically, a first etching is made as far as the upper surface of the lower insulating layer of the stack. The sides of the pillar thus formed are then protected by insulating spacers. The remaining layers of the stack are then etched, and partial lateral etching is applied to the bottom layer of gate material, which is to form the future bottom gate of the transistor. A dielectric plug is then formed on the sides of this bottom gate, then the insulating spacers are eliminated and a selective further epitaxy is carried out, as in the preceding solution, so as to form the source and drain regions in contact with the channel region.
Such a solution allows better insulation of the source and drain regions relative to the bottom gate. However, it still has the drawback of requiring a further epitaxy, which is also carried out from the substrate. Therefore, apart from the already mentioned drawbacks of a further epitaxy on particularly the form of the source and drain regions, such a solution may lead to insulation problems between the channel region and the substrate.
Furthermore, this solution also has the major drawback of controlling the dimensions of the bottom gate and the top gate at two different times, and additionally in one case by anisotropic etching and in the other case by isotropic lateral etching. Generally, the source and drain regions are implanted relative to the top gate. Consequently, if the bottom gate has a dimension offset relative to the top gate (bottom: or top dimension), the result may be a deterioration in the performance of the transistor. Furthermore, such a solution does not lead to a device that can be perfectly reproduced in respect to gauging control dependency.